This invention pertains to a method for improved surface planarity in selective epitaxial silicon. The growth of selective epitaxial silicon required to form a patterned mask on the substrate surface. The mask can be made of a single layer material such as silicon dioxide or silicon nitride. However, in certain device applications (such as sidewall base contact bipolar transistors) the mask needs to use multilayered materials which are sequentially deposited on the substrate main surface. An example of the multi-layered mask is a parallel stacking of silicon dioxide, doped polysilicon, and silicon dioxide. The mask is then patterned by the photolithographic method followed by reactive ion etching to remove certain regions defined by the lithographic pattern. The selective epitaxial growth (SEG) technique is applied to deposit silicon only inside the etched grooves but not on the mask surface. When selective epitaxial silicon is to be used for the IC device fabrication, its thickness needs to be controlled to the same height as that of the mask.
The selective epitaxial growth (SEG) of silicon is typically carried out by chemical vapor deposition at a fixed temperature. In prior art it has been observed that a planar surface is very difficult to obtain. The nonplanarity mainly occurs at the epitaxy/mask interface. There are two main non-planar surface morphologies that are a problem. One is the enhanced deposition of silicon around the edges of grooves or trenches. This morphology is often observed when the sidewalls of the mask contain polysilicon. The other is facet formation due to a slower deposition at the edges of grooves. Any of non-planar surface morphologies are not desirable for high density IC device fabrication.